1. Field of the Invention
The present invention relates generally to analog integrated circuit (IC) devices, and more particularly to an amplifier circuit for driving a capacitive load.
2. Description of the Related Art
Recently, in the manufacture of integrated circuit (IC) devices, there are no limits in requirement and demand for further improvements in the integration density and further enhancements of the performance of IC devices. In addition to such requirements, amplifier IC devices are required to attain an improved driving capability that enables them to drive an increased capacitive load while maintaining an improved frequency characteristic. Of the amplifier circuits, operational amplifiers (op amps) have wide applicability and are becoming important more and more for the semiconductor manufacturers.
A presently available operational amplifier circuit for a capacitive load drive typically includes two stages of amplifier sections. The first-stage amplifier may be a differential amplifier coupled to the second-stage amplifier section, which provides a negative feed-back path to the differential amplifier. In the feedback path from the output of the second amplifier section to that of the first amplifier section, a capacitor is inserted which performs a phase compensation for the operational amplifier circuit.
Several techniques have been studied to improve the frequency characteristic of an operational amplifier circuit for driving an increased capacitive load. One of such techniques is disclosed, for example, in Paul R. Gray and Robert G. Meyer, "Analysis and Design of Analog Integrated Circuits," John Wiley & Sons, Chapter 12, 1984. The technique disclosed therein is a "transmission zero" point shift technique that shifts or moves the zero point, by using a transistor added to an operational amplifier, from the positive polarity region (right half plane) to the negative polarity region (left half plane) in the frequency domain called the "S-plane" among those skilled in the amplifier art. The added transistor is connected in series to the phase-compensation capacitor. The transistor functions as a resistor for forcing the zero-point to be shifted in the negative polarity region. With this prior art, however, no improvements can be expected with respect to the second pole. Therefore, a large compensation capacitor is necessary to drive a large capacitive load, which leads to an undesirable decrease in the slew rate and also to an increase in circuit-occupation area on an IC chip for the operational amplifier.
Another prior art technique may be found in Bhupendra K. Ahuja, "An Improved Frequency Compensation Technique for CMOS Operational Amplifiers," IEEE Journal of Solid-State Circuits, Vol. SC-18, No. 6, Dec. 1983, at pp. 629-633. The frequency characteristic improving technique disclosed therein is different from the Gray et al's technique in that, while the Gray et al's operational amplifier includes a feedback path that feeds back a current proportional to the time-derivative of a difference between the outputs of the first- and second-stage amplifier sections, the Ahuja's operational amplifier uses a current that is proportional to the time-derivative of the output of the second amplifier section itself, as a feedback current fed back to the first-stage amplifier section, as shown in FIG. 3(a).
With the prior art, a specific frequency pole called the "second pole" can be shifted toward a higher frequency region, thereby to improve the frequency characteristic of the operational amplifier. In addition, there is no degradation of the phase characteristic, because the generation of any transmission zero point does not take place in the right half plane of the S-plane. However, the prior art suffers from an undesirable input offset voltage, which is due to a miss-match in the current value that takes place between a current source I1 being coupled to the drain side of an additional transistor and a current source I2 being coupled to the source side thereof when the output currents of these current sources I1, I2 are different from each other.
A still another frequency characteristic improving technique is disclosed in David B. Ribner and Miles A. Copeland, "Design Techniques for Cascoded CMOS Op Amps with Improved PSRR and Common-Mode Input Range," IEEE Journal of Solid-State Circuits, Vol. SC-19, No. 6, Dec. 1984, at pp. 919-925. With an operational amplifier disclosed therein, transistors are added between a differential pair and an active load, thereby reducing the impedance at the feedback node of negative feedback network. The reduced impedance allows that the feedback current approximates the proportional current to an output voltage of differential amplifier. As a result, the second pole can be shifted toward higher frequency region as in the previous case.
With such an arrangement, the added transistors are driven by a constant voltage having a fixed potential level, which is applied to the gate electrode of the added transistors. Employing such fixed bias voltage may limit the common-mode input range of the differential amplifier. In other words, using a buffer circuit having a voltage-follower circuit configuration may limit the dynamic range of input signals. In addition, the supply of the constant bias voltage requires that a bias generator circuitry is externally arranged and connected to the transistors. Such external bias generator is necessary, because, if this constant bias generator is arranged within the operational amplifier, the resultant circuit scale of the operational amplifier becomes larger, which will make it difficult to meet the requirements of attaining higher integration density.